1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In recent years, manufacturing of semiconductor devices, in which thin film transistors are formed over substrates of glass or the like having insulating surfaces and these thin film transistors are utilized as switching elements or the like, has been actively pursued. For these thin film transistors, island-shaped semiconductor layers are formed over a substrate having an insulating surface, and a part of the island-shaped semiconductor layers are utilized as channel forming regions (for example, see Patent Document 1: Japanese Published Patent Application No. H11-258636).
Pattern diagrams of a general thin film transistor are FIGS. 12A to 12C. FIG. 12A is a top diagram of the thin film transistor, FIG. 12B is a cross-sectional diagram along a dashed line O-P, and FIG. 12C is a cross-sectional diagram along a dashed line Q-R. Note that in FIG. 12A, a thin film and the like included in the thin film transistor are partially omitted.
In a thin film transistor, an island-shaped semiconductor layer 9006 is provided over a substrate 9000 with a base insulating layer 9002 therebetween. Over the semiconductor layer 9006, a conductive layer 9012 that functions as a gate electrode is formed, with a gate insulating layer 9004 interposed therebetween. Further, the semiconductor layer 9006 includes a channel formation region 9008 which is formed in a region overlapping with the conductive layer 9012 with the gate insulating layer 9004 interposed therebetween, and a source or drain region 9010.
However, in a thin film transistor including an island-shaped semiconductor layer, there is concern for various defects occurring due to an end portion of the semiconductor layer. For example, in the case of forming the semiconductor layer into an island shape, the end portion of the semiconductor layer forms a step; consequently, coverage of the end portion of the semiconductor layer with a gate insulating layer tends to be poor. For example, as shown by a dashed line 9007 in FIG. 12B, at the end portion of the semiconductor layer 9006, there is a case where the gate insulating layer 9004 becomes thin locally. In a case where sufficient coverage with the gate insulating layer cannot be performed at the end portion of the semiconductor layer, there is concern for a short circuit occurring between a conductive layer forming a gate electrode and the semiconductor layer, or a leakage current occurring. Particularly in recent years, in order to lower power consumption and to improve operation speed of thin film transistors, reduction in thickness of the gate insulating layer is desired. Consequently, when the gate insulating layer is provided to be thin, coverage defect at an end portion of a semiconductor layer becomes a pronounced problem.
Further, due to an effect of an etching process, a washing process using hydrofluoric acid (HF) or the like, or the like in forming the semiconductor layer into an island shape, an insulating layer provided under the semiconductor layer may become removed. In particular, in the case where the semiconductor layer is made into a thin film, that effect becomes prominent. In this case, as shown by a dashed line 9009 in FIG. 12C, coverage with the gate insulating layer tends to decrease near the end portion of the semiconductor layer 9006.
Further, at the end portion of the island-shape semiconductor layer, particularly at a region where the conductive layer forming the gate electrode overlaps with the semiconductor layer, electric field tends to concentrate at a corner portion (a corner). When an electric field is concentrated, there is a problem that a leaked current occurs due to dielectric breakdown or the like of the gate insulating layer, which is formed between the conductive layer forming the gate electrode and the semiconductor layer. In addition, a coverage defect of the gate insulating layer also leads to electrostatic discharge (ESD) of an element or the gate insulating layer, which becomes a factor in yield reduction in manufacturing semiconductor devices.